报告人：Yan Zhu (诸嫣) （澳门大学）
For high speed ADC designs the time-interleaving scheme is generally used. With the increased number of channels, the design challenge is focused on the ADC’s sampling front-end, as the timing mismatch among the sub-channels intrudes spurs. Some designs either implement large clock buffer chain or use complicated timing calibration that is power or area consuming. This talk covers two design topics: a wideband sampling network design to achieve more than 65dB SFDR without using any timing calibration; a single channel ADC obtaining 1GS/s sampling rate and near 10-bit ENOB.
Yan Zhu (诸嫣) (S’10- M’17) received the M.Sc. and Ph.D. degrees in electrical and electronics engineering from the University of Macau Macao, China, in 2009 and 2011, respectively. She is now an associate professor with the State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China. She received Best Paper award in ESSCIRC 2014, the Student Design Contest award in A-SSCC 2011, the Chipidea Microelectronics Prize and Macao Scientific and Technological R&D Awards in 2012, 2014 and 2016 for outstanding Academic and Research achievements in Microelectronics. She has published 70+ technical journals and conference papers in her field of interests, including 11 JSSC, 9 ISSCC papers and holds 3 US patents. Her research interests include low-power and wideband high-speed Nyquist A/D converters, PLL and image processing.